Abstract
Power-Line Communications have spread worldwide in recent years, mainly due to their increasing importance as a feasible alternative to provide broadband data access in certain domains, such as Smart Grids, Internet of Things or industrial environments in general, where the mains are available. Broadband PLC implies significant computational requirements, often related to multi-carrier modulations and high data rates that should be managed in parallel. Furthermore, these data rates also involve the necessity of specific analog front-ends (AFE), capable of tackling the corresponding high sampling frequencies in A/D and D/A converters. This work describes the design of an FPGA-based (Field-Programmable Gate Array) architecture, in charge of managing an ad-hoc AFE for broadband PLC. The proposal also implements a Filter-Bank Multi-Carrier (FBMC) modulation as medium access technique and a synchronism based on pilot sequences. A dedicated peripheral has been designed for that purpose, which has been integrated in a System-on-Chip (SoC). The proposal has been verified experimentally, validating the expected functionality.