Raúl Mateos

Latest

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms
Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture
HW/SW Architecture for a Broadband Power-Line Communication System With LS Channel Estimator and ASCET Equalizer
Arquitectura Mixta HW/SW para el Igualador de Canal L-ASCET en Comunicaciones PLC
Heterogeneous SoC Architecture for a FBMC Receiver with Channel Estimator and Channel Equalizer in PLC
Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
Dual-Core Architecture for PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer
Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLC
Modelado HLS de un Transmultiplexor Multiportadora para PLC: Comparativa dePrestaciones